AVR/InstructionSet の編集 - スーの道具箱

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*AVR Instruction Set [#z70ca3d3]

#contents

*Instruction Set [#l991e2dc]

**Arithmetic and Logic Instructions [#p3112914]

|Mnemonic|Operands|Description|Operation|Flags|Cycles|h
|ADD|Rd, Rr&#160;|Add without Carry&#160;|Rd ← Rd + Rr&#160;|Z,C,N,V,H,S&#160;|1|
|ADC|Rd, Rr|Add with Carry|Rd ← Rd + Rr + C|Z,C,N,V,H,S|1|
|ADIW|Rdl, K6|Add Immediate To Word|Rdh:Rdl ← Rdh:Rdl + K6|Z,C,N,V,S|2|
|SUB|Rd, Rr|Subtract without Carry|Rd ← Rd - Rr|Z,C,N,V,H,S|1|
|SUBI|Rd, K8|Subtract Immediate|Rd ← Rd - K8|Z,C,N,V,H,S|1|
|SBC|Rd, Rr|Subtract with Carry|Rd ← Rd - Rr - C|Z,C,N,V,H,S|1|
|SBCI|Rd, K8|Subtract with Carry Immedtiate|Rd ← Rd - K8 - C|Z,C,N,V,H,S|1|
|SBIW|Rdl, K6|Subtract Immediate from Word|Rdh:Rdl ← Rdh:Rdl - K6|Z,C,N,V,S|2|
|AND|Rd, Rr|Logical AND|Rd ← Rd ∧ Rr|Z,N,V,S&#160;|1|
|ANDI|Rd, K8|Logical AND with Immediate|Rd ← Rd ∧ K8|Z,N,V,S|1|
|OR|Rd, Rr|Logical OR|Rd ← Rd ∨ Rr|Z,N,V,S|1|
|ORI|Rd, K8|Logical OR with Immediate|Rd ← Rd ∨ K8|Z,N,V,S|1|
|EOR|Rd, Rr|Logical Exclusive OR|Rd ← Rd &#8853; Rr|Z,N,V,S|1|
|COM|Rd|One's Complement|Rd ← $FF - Rd|Z,C,N,V,S|1|
|NEG|Rd|Two's Complement|Rd ← $00 - Rd|Z,C,N,V,H,S|1|
|SBR|Rd, K8|Set Bit(s) in Register|Rd ← Rd ∨ K8|Z,C,N,V,S|1|
|CBR|Rd, K8|Clear Bit(s) in Register|Rd ← Rd ∧ ($FF - K8)|Z,C,N,V,S|1|
|INC|Rd|Increment Register|Rd ← Rd + 1|Z,N,V,S|1|
|DEC|Rd|Decrement Register|Rd ← Rd - 1|Z,N,V,S|1|
|TST|Rd|Test for Zero or Negative|Rd ← Rd ∧ Rd|Z,C,N,V,S|1|
|CLR|Rd|Clear Register|Rd ← 0|Z,C,N,V,S|1|
|SER|Rd|Set Register|Rd ← $FF||1|
|MUL|Rd, Rr|Multiply Unsigned|R1:R0 ← Rd × Rr|Z,C|2|
|MULS|Rd, Rr|Multiply Signed|R1:R0 ← Rd × Rr|Z,C|2|
|MULSU|Rd, Rr|Multiply Signed with Unsigned|R1:R0 ← Rd × Rr|Z,C|2|
|FMUL|Rd, Rr|Fractional Multiply Unsigned|R1:R0 ← (Rd × Rr) << 1|Z,C|2|
|FMULS|Rd, Rr|Fractional Multiply Signed|R1:R0 ← (Rd × Rr) << 1|Z,C|2|
|FMULSU|Rd, Rr|Fractional Multiply Signed with Unsigned|R1:R0 ← (Rd × Rr) << 1|Z,C|2|

**Branch Instructions [#g821af2b]

|Mnemonic|Operands|Description|Operation|Flags|Cycles|h
|RJMP|k|Relative Jump|PC ← PC + k + 1||2|
|IJMP||Indirect Jump to (Z)|PC ← Z||2|
|EIJMP||Extended Indirect Jump (Z)|PC(15:0) ← Z&br;PC(21:16) ← EIND||2|
|JMP|k|Jump&#160;|PC ← k||3|
|RCALL|k|Relative Call Subroutine|STACK ← PC + 1&br;PC ← PC + k + 1||3/4|
|ICALL||Indirect Call to (Z)|STACK ← PC + 1&br;PC ← Z||3/4|
|EICALL||Extended Indirect Call (Z)|STACK ← PC + 1&br;PC(15:0) ← Z&br;PC(21:16) ← EIND||4|
|CALL|k|Call Subroutine|STACK ← PC+2&br;PC ← k||4/5|
|RET||Subroutine Return|PC ← STACK||4/5|
|RETI||Interrupt Return|PC ← STACK|I|4/5|
|CPSE|Rd, Rr|Compare, Skip if equal&#160;|if  (Rd == Rr) PC ← PC + 2 or 3||2/3|
|CP|Rd, Rr|Compare|Rd - Rr|Z,C,N,V,H,S|1|
|CPC|Rd, Rr|Compare with Carry|Rd - Rr - C|Z,C,N,V,H,S|1|
|CPI|Rd, K8|Compare with Immediate|Rd - K|Z,C,N,V,H,S|1|
|SBRC|Rr, b|Skip if bit in register cleared|if (Rr(b) = 0) PC ← PC + 2 or 3||2/3|
|SBRS|Rr, b|Skip if bit in register set|if (Rr(b) = 1) PC ← PC + 2 or 3||2/3|
|SBIC|P, b|Skip if bit in I/O register cleared|if (I/O(P,b) = 0) PC ← PC + 2 or 3||2/3|
|SBIS|P, b|Skip if bit in I/O register set|if (I/O(P,b) = 1) PC ← PC + 2 or 3||2/3|
|BRBC|s, k|Branch if Status flag cleared|if (SREG(s) = 0) PC ← PC + k + 1||1/2|
|BRBS|s, k|Branch if Status flag set|if (SREG(s) = 1) PC ← PC + k + 1||1/2|
|BREQ|k|Branch if equal|if (Z = 1) PC ← PC + k + 1||1/2|
|BRNE|k|Branch if not equal|if (Z = 0) PC ← PC + k + 1||1/2|
|BRCS|k|Branch if carry set|if (C = 1) PC ← PC + k + 1||1/2|
|BRCC|k|Branch if carry cleared|if (C = 0) PC ← PC + k + 1||1/2|
|BRSH|k|Branch if same or higher|if (C = 0) PC ← PC + k + 1||1/2|
|BRLO|k|Branch if lower|if (C = 1) PC ← PC + k + 1||1/2|
|BRMI|k|Branch if minus|if (N = 1) PC ← PC + k + 1||1/2|
|BRPL|k|Branch if plus|if (N = 0) PC ← PC + k + 1||1/2|
|BRGE|k|Branch if greater than or equal (signed)|if (S = 0) PC ← PC + k + 1||1/2|
|BRLT|k|Branch if less than (signed)|if (S = 1) PC ← PC + k + 1||1/2|
|BRHS|k|Branch if half carry flag set|if (H = 1) PC ← PC + k + 1||1/2|
|BRHC|k|Branch if half carry flag cleared|if (H = 0) PC ← PC + k + 1||1/2|
|BRTS|k|Branch if T flag set|if (T = 1) PC ← PC + k + 1||1/2|
|BRTC|k|Branch if T flag cleared|if (T = 0) PC ← PC + k + 1||1/2|
|BRVS|k|Branch if overflow flag set|if (V = 1) PC ← PC + k + 1||1/2|
|BRVC|k|Branch if overflow flag cleared|if (V = 0) PC ← PC + k + 1||1/2|
|BRIE|k|Branch if interrupt enabled|if (I = 1) PC ← PC + k + 1||1/2|
|BRID|k|Branch if interrupt disabled|if (I = 0) PC ← PC + k + 1||1/2|

**Data Transfer Instructions [#e96fec0a]

|Mnemonic|Operands|Description|Operation|Flags|Cycles|h
|MOV|Rd, Rr|Copy register|Rd ← Rr||1|
|MOVW|Rdl, Rrl|Copy register pair|Rdh:Rdl ← Rrh:Rrl&br;※dl, rl even||1|
|LDI|Rd, K8|Load Immediate|Rd ← K||1|
|LDS|Rd, k|Load Direct|Rd ← (k)||2|
|LD|Rd, X|Load Indirect|Rd ← (X)||2|
|LD|Rd, X+|Load Indirect and Post-Increment|Rd ← (X)&br;X ← X + 1||2|
|LD|Rd, -X|Load Indirect and Pre-Decrement|X ← X - 1&br;Rd ← (X)||2|
|LD|Rd, Y|Load Indirect|Rd ← (Y)||2|
|LD|Rd, Y+|Load Indirect and Post-Increment|Rd ← (Y)&br;Y ← Y + 1||2|
|LD|Rd, -Y|Load Indirect and Pre-Decrement|Y ← Y - 1&br;Rd ← (Y)||2|
|LDD|Rd, Y+q|Load Indirect with displacement|Rd ← (Y + q)||2|
|LD|Rd, Z|Load Indirect&#160;|Rd ← (Z)||2|
|LD|Rd, Z+|Load Indirect and Post-Increment|Rd ← (Z)&br;Z ← Z + 1||2|
|LD|Rd, -Z|Load Indirect and Pre-Decrement|Z ← Z - 1&br;Rd ← (Z)||2|
|LDD|Rd, Z+q|Load Indirect with displacement|Rd ← (Z + q)||2|
|STS|k, Rr|Store Direct|(k) ← Rr||2|
|ST|X, Rr|Store Indirect|(X) ← Rr||2|
|ST|X+, Rr|Store Indirect and Post-Increment|(X) ← Rr&br;X ← X + 1||2|
|ST|-X, Rr|Store Indirect and Pre-Decrement|X ← X - 1&br;(X) ← Rr||2|
|ST|Y, Rr|Store Indirect|(Y) ← Rr||2|
|ST|Y+, Rr|Store Indirect and Post-Increment|(Y) ← Rr&br;Y ← Y + 1||2|
|ST|-Y, Rr|Store Indirect and Pre-Decrement|Y ← Y - 1&br;(Y) ← Rr||2|
|STD|Y+q, Rr|Store Indirect with displacement|(Y + q) ← Rr||2|
|ST|Z, Rr|Store Indirect|(Z) ← Rr||2|
|ST|Z+, Rr|Store Indirect and Post-Increment|(Z) ← Rr&br;Z ← Z + 1||2|
|ST|-Z, Rr|Store Indirect and Pre-Decrement|Z ← Z - 1&br;(Z) ← Rr||2|
|STD|Z+q, Rr|Store Indirect with displacement|(Z + q) ← Rr||2|
|LPM||Load Program Memory|R0 ← (Z)||3|
|LPM|Rd, Z|Load Program Memory|Rd ← (Z)||3|
|LPM|Rd, Z+|Load Program Memory and Post-Increment|Rd ← (Z)&br;Z ← Z + 1||3|
|ELPM||Extended Load Program Memory|R0 ← (RAMPZ:Z)||3|
|ELPM|Rd, Z|Extended Load Program Memory|Rd ← (RAMPZ:Z)||3|
|ELPM|Rd, Z+|Extended Load Program Memory and Post-Increment|Rd ← (RAMPZ:Z)&br;Z ← Z + 1||3|
|SPM||Store Program Memory|(Z) ← R1:R0||-|
|IN|Rd, P|In Port|Rd ← P||1|
|OUT|P, Rr|Out Port|P ← Rr||1|
|PUSH|Rr|Push register on Stack|STACK ← Rr||2|
|POP|Rd|Pop register from Stack|Rd ← STACK||2|

**Bit and Bit-test Instructions [#q51dd5ce]

|Mnemonic|Operands|Description|Operation|Flags|Cycles|h
|LSL|Rd|Logical shift left|C ← Rd(7)&br;Rd(7..1) ← Rd(6..0)&br;Rd(0) ← 0|Z,C,N,V,H,S|1|
|LSR|Rd|Logical shift right|C ← Rd(0)&br;Rd(6..0) ← Rd(7..1)&br;Rd(7) ← 0|Z,C,N,V,S|1|
|ROL|Rd|Rotate left through carry|C ← Rd(7)&br;Rd(7..1) ← Rd(6..0)&br;Rd(0) ← C|Z,C,N,V,H,S|1|
|ROR|Rd|Rotate right through carry|C ← Rd(0)&br;Rd(6..0) ← Rd(7..1)&br;Rd(7) ← C|Z,C,N,V,S|1|
|ASR|Rd|Arithmetic shift right|C ← Rd(0)&br;Rd(6..0) ← Rd(7..1)|Z,C,N,V,S|1|
|SWAP|Rd|Swap nibbles|Rd(3..0) ← Rd(7..4)&br;Rd(7..4) ← Rd(3..0)||1|
|BSET|s|Set flag|SREG(s) ← 1|SREG(s)|1|
|BCLR|s|Clear flag|SREG(s) ← 0|SREG(s)|1|
|SBI|P, b|Set bit in I/O register|I/O(P,b) ← 1||2|
|CBI|P, b|Clear bit in I/O register|I/O(P,b) ← 0||2|
|BST|Rr, b|Bit store from register to T|T ← Rr(b)|T|1|
|BLD|Rd, b|Bit load from register to T|Rd(b) ← T||1|
|SEC||Set carry flag|C ←1|C|1|
|CLC||Clear carry flag|C ← 0|C|1|
|SEN||Set negative flag|N ← 1|N|1|
|CLN||Clear negative flag|N ← 0|N|1|
|SEZ||Set zero flag|Z ← 1|Z|1|
|CLZ||Clear zero flag|Z ← 0|Z|1|
|SEI||Set interrupt flag|I ← 1|I|1|
|CLI||Clear interrupt flag|I ← 0|I|1|
|SES||Set signed flag|S ← 1|S|1|
|CLS||Clear signed flag|S ← 0|S|1|
|SEV||Set overflow flag|V ← 1|V|1|
|CLV||Clear overflow flag|V ← 0|V|1|
|SET||Set T-flag|T ← 1|T|1|
|CLT||Clear T-flag|T ← 0|T|1|
|SEH||Set half carry flag|H ← 1|H|1|
|CLH||Clear half carry flag|H ← 0|H|1|

**MCU Control Instructions [#deed089c]

|Mnemonic|Operands|Description|Operation|Flags|Cycles|h
|NOP||No operation|||1|
|SLEEP||Sleep|See instruction manual||1|
|WDR||Watchdog Reset|See instruction manual||1|
|BREAK||Execution Break|See instruction manual||1|

*MPU Instructions [#jc638346]

|Mnemonic|Operands|AT90S1200|ATtiny11/12&br;ATtiny15&br;ATtiny28|AT90S2323/2343&br;AT90S4414/8515&br;AT90S4434/8535&br;ATtiny22|ATtiny26|ATmega103|ATtiny13&br;ATtiny2313&br;ATtiny25/45/85&br;ATtiny24/44/84&br;ATtiny261/461/861|ATmega8&br;ATmega48/88/168&br;ATmega8515&br;ATmega8535&br;AT90PWM2/3&br;ATmega16/32&br;ATmega406&br;ATmega161&br;ATmega163/323&br;ATmega169/165/329/325/3250/649/645|ATmega162&br;ATmega64/644/640&br;AT90CAN32/64|ATmega128/1280/1281&br;AT90CAN128|ATmega2560/2561|h
|ADD|Rd, Rr&#160;|○|○|○|○|○|○|○|○|○|○|
|ADC|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|ADIW|Rdl, K6|||○|○|○|○|○|○|○|○|
|SUB|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|SUBI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|SBC|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|SBCI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|SBIW|Rdl, K6|||○|○|○|○|○|○|○|○|
|AND|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|ANDI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|OR|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|ORI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|EOR|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|COM|Rd|○|○|○|○|○|○|○|○|○|○|
|NEG|Rd|○|○|○|○|○|○|○|○|○|○|
|SBR|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|CBR|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|INC|Rd|○|○|○|○|○|○|○|○|○|○|
|DEC|Rd|○|○|○|○|○|○|○|○|○|○|
|TST|Rd|○|○|○|○|○|○|○|○|○|○|
|CLR|Rd|○|○|○|○|○|○|○|○|○|○|
|SER|Rd|○|○|○|○|○|○|○|○|○|○|
|MUL|Rd, Rr|||||||○|○|○|○|
|MULS|Rd, Rr|||||||○|○|○|○|
|MULSU|Rd, Rr|||||||○|○|○|○|
|FMUL|Rd, Rr|||||||○|○|○|○|
|FMULS|Rd, Rr|||||||○|○|○|○|
|FMULSU|Rd, Rr|||||||○|○|○|○|
|RJMP|k|○|○|○|○|○|○|○|○|○|○|
|IJMP||||○|○|○|○|○|○|○|○|
|EIJMP|||||||||||○|
|JMP|k|||||○||○|○|○|○|
|RCALL|k|○|○|○|○|○|○|○|○|○|○|
|ICALL||||○|○|○|○|○|○|○|○|
|EICALL|||||||||||○|
|CALL|k|||||○||○|○|○|○|
|RET||○|○|○|○|○|○|○|○|○|○|
|RETI||○|○|○|○|○|○|○|○|○|○|
|CPSE|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|CP|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|CPC|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|CPI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|SBRC|Rr, b|○|○|○|○|○|○|○|○|○|○|
|SBRS|Rr, b|○|○|○|○|○|○|○|○|○|○|
|SBIC|P, b|○|○|○|○|○|○|○|○|○|○|
|SBIS|P, b|○|○|○|○|○|○|○|○|○|○|
|BRBC|s, k|○|○|○|○|○|○|○|○|○|○|
|BRBS|s, k|○|○|○|○|○|○|○|○|○|○|
|BREQ|k|○|○|○|○|○|○|○|○|○|○|
|BRNE|k|○|○|○|○|○|○|○|○|○|○|
|BRCS|k|○|○|○|○|○|○|○|○|○|○|
|BRCC|k|○|○|○|○|○|○|○|○|○|○|
|BRSH|k|○|○|○|○|○|○|○|○|○|○|
|BRLO|k|○|○|○|○|○|○|○|○|○|○|
|BRMI|k|○|○|○|○|○|○|○|○|○|○|
|BRPL|k|○|○|○|○|○|○|○|○|○|○|
|BRGE|k|○|○|○|○|○|○|○|○|○|○|
|BRLT|k|○|○|○|○|○|○|○|○|○|○|
|BRHS|k|○|○|○|○|○|○|○|○|○|○|
|BRHC|k|○|○|○|○|○|○|○|○|○|○|
|BRTS|k|○|○|○|○|○|○|○|○|○|○|
|BRTC|k|○|○|○|○|○|○|○|○|○|○|
|BRVS|k|○|○|○|○|○|○|○|○|○|○|
|BRVC|k|○|○|○|○|○|○|○|○|○|○|
|BRIE|k|○|○|○|○|○|○|○|○|○|○|
|BRID|k|○|○|○|○|○|○|○|○|○|○|
|MOV|Rd, Rr|○|○|○|○|○|○|○|○|○|○|
|MOVW|Rdl, Rrl||||||○|○|○|○|○|
|LDI|Rd, K8|○|○|○|○|○|○|○|○|○|○|
|LDS|Rd, k|||○|○|○|○|○|○|○|○|
|LD|Rd, X|||○|○|○|○|○|○|○|○|
|LD|Rd, X+|||○|○|○|○|○|○|○|○|
|LD|Rd, -X|||○|○|○|○|○|○|○|○|
|LD|Rd, Y|||○|○|○|○|○|○|○|○|
|LD|Rd, Y+|||○|○|○|○|○|○|○|○|
|LD|Rd, -Y|||○|○|○|○|○|○|○|○|
|LDD|Rd, Y+q|||○|○|○|○|○|○|○|○|
|LD|Rd, Z|○|○|○|○|○|○|○|○|○|○|
|LD|Rd, Z+|||○|○|○|○|○|○|○|○|
|LD|Rd, -Z|||○|○|○|○|○|○|○|○|
|LDD|Rd, Z+q|||○|○|○|○|○|○|○|○|
|STS|k, Rr|||○|○|○|○|○|○|○|○|
|ST|X, Rr|||○|○|○|○|○|○|○|○|
|ST|X+, Rr|||○|○|○|○|○|○|○|○|
|ST|-X, Rr|||○|○|○|○|○|○|○|○|
|ST|Y, Rr|||○|○|○|○|○|○|○|○|
|ST|Y+, Rr|||○|○|○|○|○|○|○|○|
|ST|-Y, Rr|||○|○|○|○|○|○|○|○|
|STD|Y+q, Rr|||○|○|○|○|○|○|○|○|
|ST|Z, Rr|○|○|○|○|○|○|○|○|○|○|
|ST|Z+, Rr|||○|○|○|○|○|○|○|○|
|ST|-Z, Rr|||○|○|○|○|○|○|○|○|
|STD|Z+q, Rr|||○|○|○|○|○|○|○|○|
|LPM|||○|○|○|○|○|○|○|○|○|
|LPM|Rd, Z||||○||○|○|○|○|○|
|LPM|Rd, Z+||||||○|○|○|○|○|
|ELPM||||||○||||○|○|
|ELPM|Rd, Z|||||||||○|○|
|ELPM|Rd, Z+|||||||||○|○|
|SPM|||||||○|○|○|○|○|
|IN|Rd, P|○|○|○|○|○|○|○|○|○|○|
|OUT|P, Rr|○|○|○|○|○|○|○|○|○|○|
|PUSH|Rr|||○|○|○|○|○|○|○|○|
|POP|Rd|||○|○|○|○|○|○|○|○|
|LSL|Rd|○|○|○|○|○|○|○|○|○|○|
|LSR|Rd|○|○|○|○|○|○|○|○|○|○|
|ROL|Rd|○|○|○|○|○|○|○|○|○|○|
|ROR|Rd|○|○|○|○|○|○|○|○|○|○|
|ASR|Rd|○|○|○|○|○|○|○|○|○|○|
|SWAP|Rd|○|○|○|○|○|○|○|○|○|○|
|BSET|s|○|○|○|○|○|○|○|○|○|○|
|BCLR|s|○|○|○|○|○|○|○|○|○|○|
|SBI|P, b|○|○|○|○|○|○|○|○|○|○|
|CBI|P, b|○|○|○|○|○|○|○|○|○|○|
|BST|Rr, b|○|○|○|○|○|○|○|○|○|○|
|BLD|Rd, b|○|○|○|○|○|○|○|○|○|○|
|SEC||○|○|○|○|○|○|○|○|○|○|
|CLC||○|○|○|○|○|○|○|○|○|○|
|SEN||○|○|○|○|○|○|○|○|○|○|
|CLN||○|○|○|○|○|○|○|○|○|○|
|SEZ||○|○|○|○|○|○|○|○|○|○|
|CLZ||○|○|○|○|○|○|○|○|○|○|
|SEI||○|○|○|○|○|○|○|○|○|○|
|CLI||○|○|○|○|○|○|○|○|○|○|
|SES||○|○|○|○|○|○|○|○|○|○|
|CLS||○|○|○|○|○|○|○|○|○|○|
|SEV||○|○|○|○|○|○|○|○|○|○|
|CLV||○|○|○|○|○|○|○|○|○|○|
|SET||○|○|○|○|○|○|○|○|○|○|
|CLT||○|○|○|○|○|○|○|○|○|○|
|SEH||○|○|○|○|○|○|○|○|○|○|
|CLH||○|○|○|○|○|○|○|○|○|○|
|NOP||○|○|○|○|○|○|○|○|○|○|
|SLEEP||○|○|○|○|○|○|○|○|○|○|
|WDR||○|○|○|○|○|○|○|○|○|○|
|BREAK|||||||○||○|○|○|

*Instruction Set Nomenclature [#ce2a8328]

**Status Register (SREG) [#c61bfaea]

-SREG : Status register
-C : Carry flag in status register
-Z : Zero flag in status register
-N : Negative flag in status register
-V : Two's complement overflow indicator
-S : N [+] V, For signed tests
-H : Half Carry flag in the status register
-T : Transfer bit used by BLD and BST instructions
-I : Global interrupt enable/disable flag

**Registers and Operands [#bb56b9d3]

-Rd : Destination (and source) register in the register file
-Rr : Source register in the register file
-R : Result after instruction is executed
-K : Constant data (K8 = 8 bit, K6 = 6 bit)
-k : Constant address
-b : Bit in the register file or I/O register (3 bit)
-s: Bit in the status register (3 bit)
-X, Y, Z : Indirect address register&#160;(X = R27:R26, Y = R29:R28, Z = R31:R30)
-A : I/O location address
-q : Displacement for direct addressing (6 bit)

*参照・引用ページ [#f0be8365]
-http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf

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