スーの道具箱/気まぐれ日記/2005-04-20

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pwmc is
    port(
        SCS     : in        std_logic;
        SIN     : in        std_logic;
        SCLK    : in        std_logic;
        PWM     : out       std_logic_vector(0 to 47);
        CLK     : in        std_logic;
        RESET   : in        std_logic
    );
end pwmc;

architecture Behavioral of pwmc is

signal      DeltaWave   : integer range 0 to 63;

type PWMDatatype is array (0 to 3) of integer range 0 to 64;
constant    PWMData     : PWMDatatype :=(0, 1, 8, 64);

type RAMDATAtype is array (0 to 47) of integer range 0 to 3;
signal      PWMValue    : RAMDATAtype;
signal      PWMValueBuf : std_logic_vector(0 to 1);
signal      PWMValuePos : integer range 0 to 95;

begin
    FORgen: for I in 0 to 47 generate
        PWM(I) <= '1' when (PWMData(PWMValue(I)) > DeltaWave) else '0';
    end generate;

    process(SCLK, SCS, SIN, RESET) begin
        if(RESET = '0') then
            for I in 0 to 47 loop
                PWMValue(I) <= 0;
            end loop;
        elsif(SCS = '0') then
            PWMValuePos    <= 0;
        elsif(SCLK'event and SCLK = '1') then
            PWMValuePos    <= PWMValuePos + 1;
            PWMValueBuf(1) <= PWMValueBuf(0);
            PWMValueBuf(0) <= SIN;
            if PWMValuePos mod 2 = 0 then
                PWMValue(PWMValuePos / 2) <= CONV_INTEGER(PWMValueBuf);
            end if;
        end if;
    end process;

    process(CLK, RESET) begin
        if(RESET = '0') then
            DeltaWave <= 0;
        elsif(CLK'event and CLK = '1') then
            DeltaWave <= DeltaWave + 1;
        end if;
    end process;
end Behavioral;